Job Description
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!
Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.
We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results.
Opportunity Overview We are seeking a highly motivated Analog / Mixed-Signal ASIC Design Release Engineer to join our growing team. In this role, you will play a critical role in ensuring the successful release of ASIC designs for manufacturing. You will be responsible for overseeing the design to verification release process, ensuring all deliverables meet established quality standards.
All About You Responsibilities: - Review and analyze netlists generated from schematics
- Develop block models
- Utilize cell characterization tools for accurate timing and power modeling
- Prepare netlists and libraries for use by static timing and verification
- Develop and maintain Verilog test benches for functional verification
- Perform thorough design verification simulations using Cadence simulators
- Support Analog / Mixed-Signal cosimulation environments
- Analyze simulation results and identify and resolve potential design errors
- Collaborate with design engineers to debug and fix design issues
- Prepare and maintain release documentation, including design reports, timing, and verification summaries
- Scripting for test bench and custom tool development
- Participate in design reviews and provide technical expertise
- Stay up-to-date on the latest ASIC design methodologies and tools
Qualifications: - Master's degree in Electrical Engineering or a related field (MSEE preferred)
- Minimum of 5+ years of experience in Analog / Mixed-Signal ASIC design and verification
- Proven experience with netlist analysis, Verilog modeling, and test bench development
- Proficiency in Cadence simulation, verification, timing tools
- Strong understanding of analog and mixed signed design and verification methodologies
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